Expansion#

Cape Headers#

The expansion interface on the board is comprised of two headers P8 (46 pin) & P9 (46 pin). All signals on the expansion headers are 3.3V unless otherwise indicated.

Note

Do not connect 5V logic level signals to these pins or the board will be damaged.

Note

DO NOT APPLY VOLTAGE TO ANY I/O PIN WHEN POWER IS NOT SUPPLIED TO THE BOARD. IT WILL DAMAGE THE PROCESSOR AND VOID THE WARRANTY.

NO PINS ARE TO BE DRIVEN UNTIL AFTER THE SYS_RESET LINE GOES HIGH.

Connector P8#

The following tables show the pinout of the P8 expansion header. The SW is responsible for setting the default function of each pin. Refer to the processor documentation for more information on these pins and detailed descriptions of all of the pins listed. In some cases there may not be enough signals to complete a group of signals that may be required to implement a total interface.

The column heading is the pin number on the expansion header.

The GPIO row is the expected gpio identifier number in the Linux kernel.

Each row includes the gpiochipX and pinY in the format of X Y. You can use these values to directly control the GPIO pins with the commands shown below.

# to set the GPIO pin state to HIGH
debian@BeagleBone:~$ gpioset X Y=1

# to set the GPIO pin state to LOW
debian@BeagleBone:~$ gpioset X Y=0

For Example:

+---------+----------+
| Pin     | P8.03    |
+=========+==========+
| GPIO    | 1 20     |
+---------+----------+

Use the commands below for controlling this pin (P8.03) where X = 1 and Y = 20

# to set the GPIO pin state to HIGH
debian@BeagleBone:~$ gpioset 1 20=1

# to set the GPIO pin state to LOW
debian@BeagleBone:~$ gpioset 1 20=0

The BALL row is the pin number on the processor.

The REG row is the offset of the control register for the processor pin.

The MODE # rows are the mode setting for each pin. Setting each mode to align with the mode column will give that function on that pin.

NOTES:

DO NOT APPLY VOLTAGE TO ANY I/O PIN WHEN POWER IS NOT SUPPLIED TO THE BOARD. IT WILL DAMAGE THE PROCESSOR AND VOID THE WARRANTY.

NO PINS ARE TO BE DRIVEN UNTIL AFTER THE SYS_RESET LINE GOES HIGH.

P8.01-P8.02#

P8.01

P8.02

GND

GND

P8.03-P8.05#

Pin

P8.03

P8.04

P8.05

Name

GPIO1_21

GPIO1_22

GPIO1_23

BALL

J34

J35

K32

GPIO

1 21

1 22

1 23

REG

GPIO1_21_MUX

GPIO1_22_MUX

GPIO1_23_MUX

Mode 0

GPIO1_21

GPIO1_22

GPIO1_23

MODE 1

~

~

~

MODE 2

ISP0_FL_TRIG

ISP0_FLASH_TRIG

ISP0_PRELIGHT_TRIG

MODE 3

GPIO1_21

GPIO1_22

GPIO1_23

MODE 4

~

~

~

MODE 5

~

~

~

P8.06-P8.09#

Pin

P8.06

P8.07

P8.08

P8.09

Name

GPIO1_24

GPIO1_25

GPIO1_26

GPIO1_27

BALL

K33

K34

K35

K36

GPIO

1 24

1 25

1 26

1 27

REG

GPIO1_24_MUX

GPIO1_25_MUX

GPIO1_26_MUX

GPIO1_27_MUX

Mode 0

GPIO1_24

GPIO1_25

GPIO1_26

GPIO1_27

MODE 1

~

~

~

~

MODE 2

ISP0_SHUTTER_TRIG

ISP0_SHUTTER_OPEN

ISP1_FL_TRIG

ISP1_FLASH_TRIG

MODE 3

GPIO1_24

GPIO1_25

~

~

MODE 4

~

~

~

~

MODE 5

~

~

~

~

P8.10-P8.13#

Pin

P8.10

P8.11

P8.12

P8.13

Name

GPIO1_28

GPIO1_29

GPIO1_30

GPIO3_2

BALL

K37

L32

L33

C6

GPIO

1 28

1 29

1 30

3 2

REG

GPIO1_28_MUX

GPIO1_29_MUX

GPIO1_30_MUX

GPIO3_2_MUX

MODE 0

GPIO1_28

GPIO1_29

GPIO1_30

GPIO3_2

MODE 1

~

~

~

PWM0

MODE 2

ISP1_PRELIGHT_TRIG

ISP1_SHUTTER_TRIG

ISP1_SHUTTER_OPEN

~

MODE 3

~

~

~

~

MODE 4

~

~

~

~

MODE 5

~

~

~

~

P8.14-P8.16#

Pin

P8.14

P8.15

P8.16

Name

CLK_OUT_3

GPIO3_0

GPIO0_20

BALL

E29

A6

F34

GPIO

1 20

3 0

0 20

REG

CLK_OUT_3_MUX

GPIO3_0_MUX

GPIO0_20_MUX

MODE 0

BOOT_SEL3

GPIO3_0

GPIO0_20

MODE 1

CLK_OUT_3

GMAC1_RXD2

UART3_TXD

MODE 2

~

~

UART3_IR_OUT

MODE 3

GPIO1_20

~

~

MODE 4

~

~

~

MODE 5

~

~

~

P8.17-P8.19#

Pin

P8.17

P8.18

P8.19

Name

GPIO3_1

GPIO1_5

GPIO3_3

BALL

B6

B34

D6

GPIO

3 1

1 5

3 3

REG

GPIO3_1_MUX

GPIO1_5_MUX

GPIO3_3_MUX

MODE 0

GPIO3_1

GPIO1_5

GPIO3_3

MODE 1

GMAC1_RXD3

~

PWM1

MODE 2

~

~

~

MODE 3

~

~

~

MODE 4

~

DPU_COLOR_16

~

MODE 5

~

DPU1_COLOR_16

~

P8.20-P8.22#

Pin

P8.20

P8.21

P8.22

Name

GPIO1_6

GPIO1_7

GPIO1_8

BALL

C34

D34

B35

GPIO

1 6

1 7

1 8

REG

GPIO1_6_MUX

GPIO1_7_MUX

GPIO1_8_MUX

MODE 0

GPIO1_6

GPIO1_7

GPIO1_8

MODE 1

~

QSPI1_SCLK

QSPI1_SSN0

MODE 2

~

~

~

MODE 3

~

~

~

MODE 4

DPU_COLOR_17

DPU_COLOR_18

DPU_COLOR_19

MODE 5

DPU1_COLOR_17

DPU1_COLOR_18

DPU1_COLOR_19

P8.23-P8.26#

Pin

P8.23

P8.24

P8.25

P8.26

Name

GPIO1_9

GPIO1_10

GPIO1_11

GPIO1_12

BALL

A36

B36

B37

C36

GPIO

1 9

1 10

1 11

1 12

REG

GPIO1_9_MUX

GPIO1_10_MUX

GPIO1_11_MUX

GPIO1_12_MUX

MODE 0

GPIO1_9

GPIO1_10

GPIO1_11

GPIO1_12

MODE 1

QSPI1_M0_MOSI

QSPI1_M1_MISO

QSPI1_M2_WP

QSPI1_M3_HOLD

MODE 2

~

~

~

~

MODE 3

~

~

~

~

MODE 4

DPU_COLOR_20

DPU_COLOR_21

DPU_COLOR_22

DPU_COLOR_23

MODE 5

DPU1_COLOR_20

DPU1_COLOR_21

DPU1_COLOR_22

DPU1_COLOR_23

P8.27-P8.29#

Pin

P8.27

P8.28

P8.29

Name

GPIO1_15

GPIO1_16

GPIO1_14

BALL

D37

E34

D36

GPIO

1 15

1 16

1 14

REG

GPIO1_15_MUX

GPIO1_16_MUX

GPIO1_14_MUX

MODE 0

GPIO1_15

GPIO1_16

GPIO1_14

MODE 1

UART4_CTSN

UART4_RTSN

UART4_RXD

MODE 2

~

~

~

MODE 3

~

~

~

MODE 4

DPU_VSYNC

DPU_PIXELCLK

DPU_HSYNC

MODE 5

DPU1_VSYNC

DPU1_PIXELCLK

DPU1_HSYNC

P8.30-P8.32#

Pin

P8.30

P8.31

P8.32

Name

GPIO1_13

GPIO1_3

GPIO1_4

BALL

D35

D33

A34

GPIO

1 13

1 3

1 4

REG

GPIO1_13_MUX

GPIO1_3_MUX

GPIO1_4_MUX

MODE 0

GPIO1_13

GPIO1_3

GPIO1_4

MODE 1

UART4_TXD

DSP1_JTG_TDO

DSP1_JTG_TCLK

MODE 2

~

~

~

MODE 3

~

~

~

MODE 4

DPU_COLOR_EN

DPU_COLOR_14

DPU_COLOR_15

MODE 5

DPU1_COLOR_EN

DPU1_COLOR_14

DPU1_COLOR_15

P8.33-P8.35#

Pin

P8.33

P8.34

P8.35

Name

GPIO1_2

GPIO1_0

GPIO1_1

BALL

C33

E32

A32

GPIO

1 2

1 0

1 1

REG

GPIO1_2_MUX

GPIO1_0_MUX

GPIO1_1_MUX

MODE 0

GPIO1_2

GPIO1_0

GPIO1_1

MODE 1

DSP1_JTG_TDI

DSP1_JTG_TRST

DSP1_JTG_TMS

MODE 2

~

~

~

MODE 3

~

~

~

MODE 4

DPU_COLOR_13

DPU_COLOR_11

DPU_COLOR_12

MODE 5

DPU1_COLOR_13

DPU1_COLOR_11

DPU1_COLOR_12

P8.36-P8.38#

Pin

P8.36

P8.37

P8.38

Name

GPIO0_31

GPIO0_29

GPIO0_30

BALL

D32

B32

C32

GPIO

0 31

0 29

0 30

REG

GPIO0_31_MUX

GPIO0_29_MUX

GPIO0_30_MUX

MODE 0

GPIO0_31

GPIO0_29

GPIO0_30

MODE 1

~

~

~

MODE 2

~

~

~

MODE 3

~

~

~

MODE 4

DPU_COLOR_10

DPU_COLOR_8

DPU_COLOR_9

MODE 5

DPU1_COLOR_10

DPU1_COLOR_8

DPU1_COLOR_9

P8.39-P8.41#

Pin

P8.39

P8.40

P8.41

Name

GPIO0_27

GPIO0_28

GPIO0_25

BALL

D31

E31

F30

GPIO

0 27

0 28

0 25

REG

GPIO0_27_MUX

GPIO0_28_MUX

GPIO0_25_MUX

MODE 0

GPIO0_27

GPIO0_28

GPIO0_25

MODE 1

~

~

DSP0_JTG_TDO

MODE 2

I2C1_SCL

I2C1_SDA

~

MODE 3

~

~

~

MODE 4

DPU_COLOR_6

DPU_COLOR_7

DPU_COLOR_4

MODE 5

DPU1_COLOR_6

DPU1_COLOR_7

DPU1_COLOR_4

P8.42-P8.44#

Pin

P8.42

P8.43

P8.44

Name

GPIO0_26

GPIO0_23

GPIO0_24

BALL

C31

C30

D30

GPIO

0 26

0 23

0 24

REG

GPIO0_26_MUX

GPIO0_23_MUX

GPIO0_24_MUX

MODE 0

GPIO0_26

GPIO0_23

GPIO0_24

MODE 1

DSP0_JTG_TCLK

DSP0_JTG_TMS

DSP0_JTG_TDI

MODE 2

~

I2C4_SDA

QSPI1_SSN1

MODE 3

~

~

~

MODE 4

DPU_COLOR_5

DPU_COLOR_2

DPU_COLOR_3

MODE 5

DPU1_COLOR_5

DPU1_COLOR_2

DPU1_COLOR_3

P8.45-P8.46#

Pin

P8.45

P8.46

Name

GPIO0_21

GPIO0_22

BALL

F36

D29

GPIO

0 21

0 22

REG

GPIO0_21_MUX

GPIO0_22_MUX

MODE 0

GPIO0_21

GPIO0_22

MODE 1

UART3_RXD

DSP0_JTG_TRST

MODE 2

UART3_IR_IN

I2C4_SCL

MODE 3

~

~

MODE 4

DPU_COLOR_0

DPU_COLOR_1

MODE 5

DPU1_COLOR_0

DPU1_COLOR_1

Connector P9#

The following tables show the pinout of the P9 expansion header. The SW is responsible for setting the default function of each pin. Refer to the processor documentation for more information on these pins and detailed descriptions of all of the pins listed. In some cases there may not be enough signals to complete a group of signals that may be required to implement a total interface.

The column heading is the pin number on the expansion header.

The GPIO row is the expected gpio identifier number in the Linux kernel.

Each row includes the gpiochipX and pinY in the format of X Y. You can use these values to directly control the GPIO pins with the commands shown below.

# to set the GPIO pin state to HIGH
debian@BeagleBone:~$ gpioset X Y=1

# to set the GPIO pin state to LOW
debian@BeagleBone:~$ gpioset X Y=0

For Example:

+---------+----------+
| Pin     | P9.11    |
+=========+==========+
| GPIO    | 1 1      |
+---------+----------+

Use the commands below for controlling this pin (P9.11) where X = 1 and Y = 1

# to set the GPIO pin state to HIGH
debian@BeagleBone:~$ gpioset 1 20=1

# to set the GPIO pin state to LOW
debian@BeagleBone:~$ gpioset 1 20=0

The BALL row is the pin number on the processor.

The REG row is the offset of the control register for the processor pin.

The MODE # rows are the mode setting for each pin. Setting each mode to align with the mode column will give that function on that pin.

If included, the 2nd BALL row is the pin number on the processor for a second processor pin connected to the same pin on the expansion header. Similarly, all row headings starting with 2nd refer to data for this second processor pin.

NOTES:

DO NOT APPLY VOLTAGE TO ANY I/O PIN WHEN POWER IS NOT SUPPLIED TO THE BOARD. IT WILL DAMAGE THE PROCESSOR AND VOID THE WARRANTY.

NO PINS ARE TO BE DRIVEN UNTIL AFTER THE SYS_RESET LINE GOES HIGH.

P9.01-P9.05#

P9.01

P9.02

P9.03

P9.04

P9.05

GND

GND

VOUT_3V3

VOUT_3V3

VIN

P9.06-P9.10#

P9.06

P9.07

P9.08

P9.09

P9.10

VIN

VOUT_SYS

VOUT_SYS

ONKEY#

RESET#

P9.11-P9.13#

Pin

P9.11

P9.12

P9.13

Name

UART1_TXD

QSPI0_CSN0

UART1_RXD

BALL

M32

H1

M33

GPIO

0 10

2 3

0 11

REG

UART1_TXD_MUX

QSPI0_CSN0_MUX

UART1_RXD_MUX

MODE 0

UART1_TXD

QSPI0_SSN0

UART1_RXD

MODE 1

~

PWM1

~

MODE 2

~

I2S_SDA1

~

MODE 3

GPIO0_10

GPIO2_3

GPIO0_11

MODE 4

~

~

~

MODE 5

~

~

~

P9.14-P9.16#

Pin

P9.14

P9.15

P9.16

Name

QSPI0_D1_MISO

QSPI0_D2_WP

QSPI0_D0_MOSI

BALL

K3

K2

J3

GPIO

2 6

2 7

2 5

REG

QSPI0_D1_MISO_MUX

QSPI0_D2_WP_MUX

QSPI0_D0_MOSI_MUX

MODE 0

QSPI0_M1_MISO

QSPI0_M2_WP

QSPI0_M0_MOSI

MODE 1

PWM4

PWM5

PWM3

MODE 2

I2S_MCLK

I2S_SCLK

I2S_SDA3

MODE 3

GPIO2_6

GPIO2_7

GPIO2_5

MODE 4

~

~

~

MODE 5

~

~

~

P9.17-P9.19#

Pin

P9.17

P9.18

P9.19

Name

QSPI1_CSN0

QSPI1_D0_MOSI

I2C2_SCL

BALL

H32

G35

G4

GPIO

0 1

0 2

2 9

REG

QSPI1_CSN0_MUX

QSPI1_D0_MOSI_MUX

I2C2_SCL_MUX

MODE 0

QSPI1_SSN0

QSPI1_M0_MOSI

I2C2_SCL

MODE 1

~

ISO7816_CVCC_EN

UART2_TXD

MODE 2

I2S_MCLK

I2C5_SDA

~

MODE 3

GPIO0_1

GPIO0_2

GPIO2_9

MODE 4

EFUSE_SPI_NSS

EFUSE_SPI_SI

~

MODE 5

~

~

~

P9.20-P9.22#

Pin

P9.20

P9.21

P9.22

Name

I2C2_SDA

QSPI1_D1_MISO

QSPI1_SCLK

BALL

G3

G34

H34

GPIO

2 10

0 3

0 0

REG

I2C2_SDA_MUX

QSPI1_D1_MISO_MUX

QSPI1_SCLK_MUX

MODE 0

I2C2_SDA

QSPI1_M1_MISO

QSPI1_SCLK

MODE 1

UART2_RXD

ISO7816_CLK

ISO7816_DET

MODE 2

~

~

~

MODE 3

GPIO2_10

GPIO0_3

GPIO0_0

MODE 4

~

EFUSE_SPI_SO

EFUSE_SPI_CLK

MODE 5

~

~

~

P9.23-P9.25#

Pin

P9.23

P9.24

P9.25

Name

QSPI0_D3_HOLD

QSPI1_D2_WP

GPIO2_18

BALL

K1

G33

F5

GPIO

2 8

0 4

2 18

REG

QSPI0_D3_HOLD_MUX

QSPI1_D2_WP_MUX

GPIO2_18_MUX

MODE 0

QSPI0_M3_HOLD

QSPI1_M2_WP

GPIO2_18

MODE 1

~

ISO7816_RST

GMAC1_TX_CLK

MODE 2

I2S_WS

UART5_TXD

~

MODE 3

GPIO2_8

GPIO0_4

~

MODE 4

~

EFUSE_BUSY

~

MODE 5

~

~

~

P9.26-P9.28#

Pin

P9.26

P9.27

P9.28

Name

QSPI1_D3_HOLD

GPIO2_19

SPI_CSN

BALL

F37

E4

E3

GPIO

0 5

2 19

2 15

REG

QSPI1_D3_HOLD_MUX

GPIO2_19_MUX

SPI_CSN_MUX

MODE 0

QSPI1_M3_HOLD

GPIO2_19

SPI_SSN0

MODE 1

ISO7816_DAT

GMAC1_RX_CLK

UART2_RXD

MODE 2

UART5_RXD

~

UART2_IR_IN

MODE 3

GPIO0_5

~

GPIO2_15

MODE 4

~

~

~

MODE 5

~

~

~

P9.29-P9.31#

Pin

P9.29

P9.30

P9.31

Name

SPI_MISO

SPI_MOSI

SPI_SCLK

BALL

F1

F2

D3

GPIO

2 17

2 16

2 14

REG

SPI_MISO_MUX

SPI_MOSI_MUX

SPI_SCLK_MUX

MODE 0

SPI_MISO

SPI_MOSI

SPI_SCLK

MODE 1

~

~

UART2_TXD

MODE 2

~

~

UART2_IR_OUT

MODE 3

GPIO2_17

GPIO2_16

GPIO2_14

MODE 4

~

~

~

MODE 5

~

~

~

P9.32-P9.40#

P9.32

P9.34

VDD_ADC

GND

P9.33

P9.35

P9.36

P9.37

P9.38

P9.39

P9.40

ADC_VIN_CH4

ADC_VIN_CH6

ADC_VIN_CH5

ADC_VIN_CH2

ADC_VIN_CH3

ADC_VIN_CH0

ADC_VIN_CH1

P9.41-P9.42#

Pin

P9.41

P9.42

Name

GPIO2_13

QSPI0_SCLK

BALL

D2

H3

GPIO

2 13

2 2

REG

GPIO2_13_MUX

QSPI0_SCLK_MUX

MODE 0

GPIO2_13

QSPI0_SCLK

MODE 1

SPI_SSN1

PWM0

MODE 2

~

I2S_SDA0

MODE 3

~

GPIO2_2

MODE 4

~

~

MODE 5

~

~

P9.43-P9.46#

P9.43

P9.44

P9.45

P9.46

GND

GND

GND

GND

mikroBUS#

Pin

mikroBUS port

Pin

ADC_VIN_CH7

AN

PWM

QSPI0_CSN1 (MODE1:PWM2)

AUDIO_PA3 (MODE3:GPIO4_3)

RST

INT

GPIO2_21 (MODE0:GPIO2_21)

GPIO2_20 (MODE0:GPIO2_20)

CS

RX

UART3_RXD (MODE1:UART3_RXD)

SPI_SCLK (MODE0:SPI_SCLK)

SCK

TX

UART3_TXD (MODE1:UART3_TXD)

SPI_MISO (MODE0:SPI_MISO)

MISO

SCL

GPIO0_18 (MODE1:I2C4_SCL)

SPI_MOSI (MODE0:SPI_MOSI)

MOSI

SDA

GPIO0_19 (MODE1:I2C4_SDA)

3.3V supply

3V3

5V

5V supply

Ground

GND

GND

Ground